library ieee;
use ieee.std_logic_1164.all;

entity LAcpuTest is
	port (
		-- clock
		CLOCK_27            : in    std_logic;
		-- switches
		SW      						: in    std_logic_vector(17 downto 0);
		-- the push keys
		KEY      						: in    std_logic_vector(3 downto 0);
		-- the 7seg display
		HEX0								:	out		std_logic_vector(6 downto 0);
		HEX1								:	out		std_logic_vector(6 downto 0);
		HEX2								:	out		std_logic_vector(6 downto 0);
		HEX3								:	out		std_logic_vector(6 downto 0);
		HEX4								:	out		std_logic_vector(6 downto 0);
		HEX5								:	out		std_logic_vector(6 downto 0);
		HEX6								:	out		std_logic_vector(6 downto 0);
		HEX7								:	out		std_logic_vector(6 downto 0);
		-- GPIO
		GPIO_0							: out std_logic_vector(35 downto 0);
		GPIO_1							: out std_logic_vector(35 downto 0);
		-- the leds
		LEDG             		: out   std_logic_vector(8 downto 0)
	);
end LAcpuTest;

architecture behavioral of LAcpuTest is

	component cpu
		port (
			-- clock signal
			cpuCLK					:		in	std_logic;
			ramCLK					:		in	std_logic;
			-- reset for processor
			nReset			:		in	std_logic;
			-- halt for processor
			halt				:		out	std_logic;
			-- start mmio addins
			-- dip switch in
			dipIn						:		in	std_logic_vector(15 downto 0);
			-- hexout
			hexOut					:		out	std_logic_vector(31 downto 0);
			-- end mmio addins
			-- address to dump
			dumpAddr : in std_logic_vector(15 downto 0);
			-- signals to send to LA
			toLA0		: out std_logic_vector(14 downto 0);
			toLA1		: out std_logic_vector(14 downto 0)
		);
	end component;

	-- 7segment display decoder
	component bintohexDecoder
		port (
			input		:		in	std_logic_vector(3 downto 0);
			output	:		out	std_logic_vector(6 downto 0));
	end component;

	-- signals here
	signal imemAddr				:	std_logic_vector (31 downto 0);
	signal imemData				:	std_logic_vector (31 downto 0);
	signal dmemAddr				:	std_logic_vector (31 downto 0);
	signal dmemDataRead		:	std_logic_vector (31 downto 0);
	signal dmemDataWrite	:	std_logic_vector (31 downto 0);
	signal dpaddr					:	std_logic_vector (15 downto 0);
	signal dipin					:	std_logic_vector (15 downto 0);
	signal hexout					:	std_logic_vector (31 downto 0);

	-- signals for LA
	signal toLA0: std_logic_vector(14 downto 0);
	signal toLA1: std_logic_vector(14 downto 0);
begin

	cpu_comp : cpu port map (
		cpuCLK       		=> CLOCK_27,
		ramCLK       		=> CLOCK_27,
		nReset    		=> KEY (3),
		halt      		=> LEDG (8),
		dipIn					=> dipin,
		hexOut				=> hexout,
		dumpAddr			=> dpaddr,
		toLA0				=> toLA0,
		toLA1				=> toLA1);

	--port map decoders to show address:
	--BTH0: bintohexDecoder port map (dmemDataRead (3 downto 0), HEX0);
	--BTH1: bintohexDecoder port map (dmemDataRead (7 downto 4), HEX1);	
	--BTH2: bintohexDecoder port map (dmemDataRead (11 downto 8), HEX2);
	--BTH3: bintohexDecoder port map (dmemDataRead (15 downto 12), HEX3);
	--BTH4: bintohexDecoder port map (dmemDataRead (19 downto 16), HEX4);
	--BTH5: bintohexDecoder port map (dmemDataRead (23 downto 20), HEX5);
	--BTH6: bintohexDecoder port map (dmemDataRead (27 downto 24), HEX6);
	--BTH7: bintohexDecoder port map (dmemDataRead (31 downto 28), HEX7);

	-- mmio output
	BTH0: bintohexDecoder port map (hexout(3 downto 0), HEX0);
	BTH1: bintohexDecoder port map (hexout(7 downto 4), HEX1);	
	BTH2: bintohexDecoder port map (hexout(11 downto 8), HEX2);
	BTH3: bintohexDecoder port map (hexout(15 downto 12), HEX3);
	BTH4: bintohexDecoder port map (hexout(19 downto 16), HEX4);
	BTH5: bintohexDecoder port map (hexout(23 downto 20), HEX5);
	BTH6: bintohexDecoder port map (hexout(27 downto 24), HEX6);
	BTH7: bintohexDecoder port map (hexout(31 downto 28), HEX7);

	-- address to dump
	--dpaddr <= SW (15 downto 0);
	dpaddr <= (others => '0');
	-- mmio dip switches
	dipin <= SW (15 downto 0);

	-- Export LA signals to expansion ports
	-- Work around differential signals/connector spacing, etc.

	process(toLA0, toLA1)
	begin
	GPIO_0(35 downto 0) <= (35 downto 0 => '0');
	GPIO_1(35 downto 0) <= (35 downto 0 => '0');

	GPIO_0(1) <= toLA0(0);
	GPIO_0(3) <= toLA0(1);
	GPIO_0(5) <= toLA0(2);
	GPIO_0(7) <= toLA0(3);
	GPIO_0(9) <= toLA0(4);
	GPIO_0(11) <= toLA0(5);
	GPIO_0(13) <= toLA0(6);
	-- account for space between analyzer probes
	GPIO_0(17) <= toLA0(7);
	GPIO_0(19) <= toLA0(8);
	GPIO_0(21) <= toLA0(9);
	GPIO_0(23) <= toLA0(10);
	GPIO_0(25) <= toLA0(11);
	GPIO_0(27) <= toLA0(12);
	GPIO_0(29) <= toLA0(13);
	-- account for space between analyzer probes
	GPIO_0(33) <= toLA0(14);

	GPIO_1(1) <= toLA1(0);
	GPIO_1(3) <= toLA1(1);
	GPIO_1(5) <= toLA1(2);
	GPIO_1(7) <= toLA1(3);
	GPIO_1(9) <= toLA1(4);
	GPIO_1(11) <= toLA1(5);
	GPIO_1(13) <= toLA1(6);
	-- account for space between analyzer probes
	GPIO_1(17) <= toLA1(7);
	GPIO_1(19) <= toLA1(8);
	GPIO_1(21) <= toLA1(9);
	GPIO_1(23) <= toLA1(10);
	GPIO_1(25) <= toLA1(11);
	GPIO_1(27) <= toLA1(12);
	GPIO_1(29) <= toLA1(13);
	-- account for space between analyzer probes
	GPIO_1(33) <= toLA1(14);

	end process;
end behavioral;

